Weight-Four Parity Checks Arrive on a Shuttling Silicon Spin Qubit Array

Silicon spins take a QEC-shaped step

Researchers have demonstrated weight-four parity checks on a five-qubit silicon spin processor that uses coherent spin shuttling for connectivity, reporting results in Nature (published July 29, 2026). The work shows that sparse, mobile spin-qubit arrays can execute stabilizer measurements relevant to surface-code error correction without requiring charge sensing at every qubit site.

The team reports a five-qubit Greenberger–Horne–Zeilinger (GHZ) state with verified genuine entanglement — among the largest such states constructed with gate-defined semiconductor spins — and parity-check accuracies up to 72.2% for weight-four Z-type checks.

Architecture: a shuttle bus with four stops

The device is electrostatically defined in an isotopically purified 28Si/SiGe quantum well. It contains three functional zones:

• A readout zone using parity-mode Pauli spin blockade and an RF reflectometry sensor.
• A shuttling bus along which qubits move coherently.
• Four bus stops where data qubits can interact with a mobile ancilla.

An on-chip cobalt micromagnet provides an inhomogeneous magnetic field so qubits can be addressed without an external field during operation. The ancilla qubit shuttles along the bus at roughly 1.8 m s⁻¹, interacting with data qubits at each stop.

This connectivity graph forms a weight-four stabilizer plaquette — the local building block used in surface-code memory experiments.

Remote tuning without local charge sensing

A central engineering contribution is remote tuning: because direct charge sensing reaches only the nearest bus stop, the team calibrates distant qubits by shuttling a spin in superposition and using tunneling events as phase probes. That protocol populates and controls the array without charge sensors at every site.

The authors argue this scales modularly: with shuttling coherence already demonstrated over ~10 μm, a single sensor and ohmic contact could tune on the order of 100 qubits in prototype industrial layouts.

Parity checks and entanglement benchmarks

Using a decoupled controlled-Z (DCZ) gate that refocuses shuttling-induced phases, the team implemented X- and Z-type parity checks for weights two through four. Weight-four Z-type checks on prepared eigenstates achieved 72.2(6)% accuracy; X-type checks reached 67.0(7)%.

GHZ-state fidelities across qubit combinations reached up to 76.6(1.6)% after error mitigation. Post-selecting ancilla measurement outcomes, the group initialized a [[4, 1, 2]] surface-code logical state with 62.9(1.8)% fidelity.

The paper's error budget attributes most infidelity to two-qubit exchange noise, with shuttling and idling contributing roughly a quarter — suggesting faster shuttling as the most direct improvement path.

Why this differs from July's IBM advantage headlines

IBM and collaborators published separate quantum advantage demonstrations in late July 2026 using superconducting processors and verification frameworks such as doped Clifford sampling. This Nature result is complementary: it advances semiconductor spin hardware toward the repeated stabilizer measurements fault-tolerant computing requires, rather than claiming a classical separation on a sampling task.

The authors highlight near-term feasibility for error-detecting codes such as [[4, 2, 2]] rotated toric codes on an expanded version of the same architecture.

Takeaway

Spin shuttling is no longer only a transport demo. With weight-four parity checks and multi-qubit entanglement on a five-qubit array — tuned without pervasive charge sensing — silicon spins look closer to the calibration and connectivity patterns fault-tolerant QEC will demand.

Sources

• Nature — Weight-four parity checks in a spin-shuttling architecture (July 29, 2026)
• arXiv — Weight-four parity checks with silicon spin qubits (2026)